The present invention relates to a flat panel driving circuit for driving a display panel of a line scanning type having a two-dimensional structure such as a liquid crystal panel, a plasma display, and an electroluminescence panel, and in particular, to a liquid crystal driving circuit suitable for an operation when a screen to be displayed is smaller than the screen size of the crystal panel.
As conventional flat panel driving circuits to drive the liquid crystal, there is known a liquid crystal controller HD63645F/HD64645F (to be simply referred to as LCTC herebelow) described in the Hitachi Microcomputer System LCD Timing Controller (LCTC) HD63645F/HD64645F User's Manual and a video interface controller described in the Japanese Patent Unexamined Publication JP-A-61-174595. According to these controllers, display data for a screen is stored in a frame memory such that the information thus stored is sequentially read out therefrom so as to be supplied to a liquid crystal panel together with a liquid crystal drive signal, thereby displaying the screen image on the crystal panel. In these liquid crystal controllers, however, consideration has not been given to the case where the size of the screen of the liquid crystal panel is greater than the display screen size.
Operations of the conventional liquid crystal controller will be described in detail by use of FIGS. 1 to 4. FIG. 1 shows a block diagram of a conventional liquid crystal display apparatus comprising an address generator 1, a display address signal 2, signals 3 to 5 for driving a liquid crystal panel, a line clock 3, a first line signal 4, and a data shift clock 5. The configuration further includes a frame memory 6 for storing therein display data for a screen, liquid crystal display data read from the frame memory 6 according to the display address 2, and a liquid crystal panel 8 for displaying the liquid crystal display data 7 as visible information. FIG. 2 is a signal timing chart showing operations of the crystal display apparatus of FIG. 1. FIG. 3 is a diagram showing relationships between the frame memory 6 and the liquid crystal panel 8; whereas FIG. 4 is a diagram illustrating relationships between the frame memory 6 and the liquid crystal panel 8 in a case where the size of the liquid crystal panel 8 is larger than the display area.
In the system of FIG. 1, the address generator 1 generates a display address for a screen and sends the display address 2 to the frame memory 6. The frame memory 6 outputs as liquid crystal display data 7 display data stored at an address indicated by the display address 2; in consequence, assuming that the liquid crystal display data 7 includes 4-bit parallel data, in a case of a display of, for example, 640.times.400 dots, the address generator 1 sequentially generates 64000 (640.times.400.div.4=64000) addresses ranging from OH (hexadecimal) to F9FFH (hexadecimal), which are then supplied therefrom to the frame memory 6. The frame memory 6 outputs 64000 data items as the liquid crystal display data 7 according to the addresses thus produced. The liquid crystal display data 7 is, as shown in FIG. 2, transmitted to the liquid crystal panel together with the data shift clock 5, the line clock 3, and the first line signal 4 respectively outputted from the address generator 1.
Referring now to FIG. 2, description will be given of the display operation of the liquid crystal panel 8. The liquid crystal panel 8 receives data at a rising edge of the data shift clock 5. Concretely, on receiving data for a display line, namely, 160 liquid crystal display data items 7 ranging from data item 0 to data item 159, the liquid crystal panel 8 displays the data for a line in response to the line clock 3. When this operation is repeatedly effected 400 times, control returns to the first line. The first line signal 4 designating which one of data items corresponds to the first line is, as shown in FIG. 2, outputted at a timing when the signal 4 becomes high in response to an output of the line clock 3 displaying the data of the first line, thereby accomplishing the data display for the first line. In consequence, as for the relationship between the data in the frame memory and that displayed on the liquid crystal panel 8, information stored in the frame memory 6 is directly displayed on the crystal panel 8 as shown in FIG. 3.
According to the prior art technology above, considerations have not been given to a case where a data area to be displayed is smaller than the liquid crystal panel 8. That is, for example, in a case where 640.times.400 dots are to be displayed on a panel having 640.times.480 dots, and in particular, where the display of 640.times.400 dots is effected on the center of the liquid crystal panel 8, it is necessary to respectively store margin data of 40 lines, as shown in FIG. 4, in the upper and lower portions of the display data of 640.times.400 dots in the frame memory 6 such that the data are sequentially read from the frame memory 6 so as to display the data on the liquid crystal panel 8. In this display method, however, when the operation speed of the liquid crystal display apparatus is taken into consideration, in a case where the display of 640.times.400 dots is achieved by use of a panel of 640.times.400 dots, although a frame frequency of 70 Hz can be developed through an operation at a rate of 18 MHz/dot, if a panel of 640.times.480 dots is used in this case, the frame frequency becomes 58 Hz for the conventional 18 MHz/dot operation and hence beyond the operation range 65 to 75 Hz of the liquid crystal, namely, if the frame frequency of 70 Hz is developed, a 21.5 MHz/dot operation becomes necessary, which leads to a problem that a high-speed device is required when the panel of 640.times.400 dots is used.